A 0.007mm2 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator

This work presents a fully integrated three-stage low-dropout regulator (LDO) for system-on-chip applications. The circuit is compensated with the reverse nested miller technique using current buffers (RNMCCB). Based on the results of a complementary Pole-Zero analysis, and the biasing of the power transistor in the triode region, it was possible to size the LDO such that the lowest reported area is achieved for loads up to 50mA. A dynamic biasing circuit is used to speed up the transient response and minimize the settling time. The regulator has been implemented in a TSMC 130nm CMOS technology and occupies an active chip area of 0.007 mm
²
including the capacitors.