Low Power High Speed Dynamic Comparator

In this study, we proposed a novel technique to enhance the performance of the dynamic comparator. The pre-amplifier outputs are directly connected to the latching nodes through switches that are controlled by output logics. Hence, the path of static current will be disconnected after making decision. Comparing to the previous dynamic comparators, the proposed structure shows significant performance improvement. The comparator has been simulated in standard 90nm technology. Simulation results show that the proposed comparator is suitable for low power, high speed applications.