Extra Bit Generation for High-Speed Time-Based Flash ADCs in 65nm CMOS

A time-based, low-power and low-offset 5-bit 1GS/s Flash analog to digital converter (ADC) is presented in this paper. To decrease the static offset of the comparators and to increase ADC resolution, an offset cancellation technique is incorporated. Moreover, the last bit is generated without using an extra comparator in order to further reduce the impact of statistics offsets. Proposed ADC can achieve 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests are equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC is designed in TSMC 65nm CMOS technology and consumes 7.7 mW at 1 GHz sampling frequency achieving 415-fJ/convstep figure of merit.