Layout-dependent effects aware gm/iD-based many-objective sizing optimization for analog integrated circuits

Layout-dependent effects (LDEs) as one type of second-order effects in addition to parasitics, the primary second-order effect, are considered in our proposed two-stage hybrid sizing methodology for analog circuits. The first-stage sizing optimization is realized by using gm/ID-based symbolic modeling and nonlinear programming. A many-objective evolutionary algorithm based sizing refiner works for the second-stage optimization. MOSFET characterization and considerations of intrinsic and interconnect parasitics as well as LDEs are addressed progressively throughout the proposed hybrid sizing flow. Finally, the experimental results demonstrate high efficacy of our proposed gm/ID-based parasitic-aware and LDE-aware two-stage sizing methodology.