A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor

A 10 GHz bang-bang all-digital phase-locked loop (BB-ADPLL) is proposed for high-speed wireline communication. A novel high resolution fractional capacitor is proposed in LC-DCO, which overcomes the process limitation of MOM capacitors and raises Q factor. The resolution of DCO is improved more than ten times and the Q factor of the LC-tank increases two times. The ADPLL is fabricated in 65 nm CMOS process. The phase noise of the proposed 10 GHz ADPLL is -95.7 dBc/Hz @ 1 MHz offset and the RMS jitter is 0.88 ps (1 kHz to 100 MHz). The ADPLL consumes 10.5 mW from a 1.2 V supply voltage and occupies an active area of 0.06 mm².