Design Trade-offs in Buck Converters for Low-Energy Wireless Transceivers

Energy consumed at startup from sleep mode constrains the design of DC-DC converters in low duty-cycle applications. This paper presents a startup technique and design methodology to preserve the converter's energy efficiency. A replica circuit is employed to achieve a constant startup time across supply and process corners. The proposed technique has a negligible quiescent current and area overhead. A Pulse Frequency Modulation (PFM) control scheme is implemented using UMC130nm CMOS technology. The regulator generates a 3.5mV voltage ripple with 1mV variations from a 1.6V to 3.6V input supply. It can supply a load current ranging from 1mA to 22.5mA. A new Figure of Merit (FoM) is introduced to allow comparison between different PFM buck converters in terms of the voltage ripple, switching frequency and energy efficiency.