A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion

The idea of recycling part of the charge used to drive a load is well understood in digital circuits, and falls under the umbrella term of charge recovery logic (CRL). By recovering part of the charge from the load, these circuits achieve lower energy consumption with respect to static CMOS. Recently, a comparator that uses the principles of charge recovery was presented, introducing these energy advantages to the world of mixed-signal circuits. The original design has a maximum operating frequency of 1 kHz, and thus is limited to niche applications. In this work, an improved charge recovery comparator is introduced, operating at up to 900 MHz. Post-layout simulations in 65 nm technology show an energy consumption of 40 fJ per conversion, and an input offset voltage of 32 mV.