Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC

Time interleaving is one of the prominent ways to increase the operating speed of data converters. However, mis-match artifacts among the time interleaving sections impair the performance benefits obtained from the use of time interleaving. CTDSMs with time interleaved quantizers are particularly affected by the gain mismatch in the time interleaved feedback DAC. We present a circuit technique to eliminate this adverse effect of the gain mismatch between time interleaved sections in 2×-time interleaved quantizers. The proposed technique involves the use of a three state DAC as a feedback DAC element. The simulations results obtained from the schematic level implementation of the proposed three state DAC in 40nm CMOS process demonstrate the efficacy of the presented idea.