A 2MS/s, 11.22 ENOB, 3.2 Vpp-d SAR ADC with improved DNL and offset calculation

A 12-bit SAR ADC with an extended input range of 3.2 Vpp-d (±1.33 VREF) achieved through the use of an input sampling scaling technique, is presented. The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The ADC is implemented in a 0.13 μm CMOS process and achieves an SNDR of 69.3 dB and an SFDR of 79 dB without calibration, while consuming 0.9 mW, with a measured DNL of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.