A fault tolerant dynamically scheduled processor with partial permanent fault handling

This paper describes architectural extensions for a dynamically scheduled processor, in order to make it almost completely fault-tolerant against single event upsets. The base architecture is a Tomasulo architecture, whose sphere of replication covers the most relevant data path elements, in order to protect them from temporary and permanent faults by concurrent execution. Nevertheless, some critical signals of the data path and all components outside the data path remain still sensitive to faults. For that reason an additional recovery mechanism was implemented that causes a re-execution of already fetched instructions, if errors are detected in the critical signals and components outside the sphere of replication. We describe how to extend these components with simple error detection techniques that can trigger the recovery mechanism. It turned out that with that combination the processor can be protected against almost all transient faults by only 20 % hardware overhead according to the used fault model. Furthermore we investigate the robustness of the approach against permanent faults.