Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP

In this paper, the effects of application-specific instruction-set processor (ASIP) hardware optimizations on the performance of beamforming algorithms and on the hardware requirements (i.e., silicon area and power consumption) are studied. For that, the performance of three beamforming algorithms with different fixed-point implementations are compared using objective instrumental measures, i.e., PESQ, STOI, and iSNR. The proposed application-specific hardware optimizations are implemented in a VLIW-SIMD hearing aid processor, modifying the processor's datapath width, using a co-processor for the division operation and applying register file power optimizations. In total 24 different optimized processor configurations are studied. The result of this evaluation is that the same processor, running one of the beamformers, can be optimized, decreasing up to 2 times the silicon area requirements or up to 11 times the power consumption, thereby only slightly decreasing the overall algorithm performance (e.g., −2dB iSNR for a fixed beamformer).