An improved analysis of dv/dt-induced low-side MOSFET false turn on in synchronous Buck converters

This paper presents new studies of dv/dt-induced low-side MOSFET false trigger when the high-side MOSFET is turned on in synchronous Buck converters. New analytical expressions are derived and utilized to predict both the magnitude and duration of the false triggering pulse for more accurate power loss calculation. The proposed model takes into account effects of nonlinear time-varying nature of the low-side MOSFET dv/dt during the high-side MOSFET turn on transition, the low-side MOSFET body-diode reverse-recovery current and common-source inductance. The model is mostly suitable for low-voltage applications in which false turn on of the low-side MOSFET could happen more often than under high-voltage conditions due to lower MOSFET threshold voltage, higher di/dt, and stronger gate drivers. The model is tested on a 12V to 1.35V, 8A converter, and predictions are compared with experimental data with good correlation.