Ver2Smv — A tool for automatic verilog to SMV translation for verifying digital circuits

Verification of today's complex digital circuit designs is of critical concern for hardware designers. A tremendous amount of effort and computing resources are spent to assure if the developed design is correct or not. Simulation is by far the most extensively used method for this purpose. However, it does not provide 100% coverage of the possible test patterns. Formal verification tends to overcome these limitations. However, digital circuits are usually described in Verilog/VHDL and these descriptions need to be manually expressed in a formal language for their formal verification. This is a cumbersome task and thus limits the usage of formal verification in the industrial setting. This paper presents a step towards overcoming these problems by presenting a tool, Ver2Smv, for automatically translating RTL Verilog to the SMV language, i.e., a language supported by the NuXmv model checker. Besides the Verilog description, the user provides a VCD format file (random stimulus data) through a user friendly Python interface. This file helps in the automatic specification generation as assertions and relieves the user from writing them manually. These assertions are verified using the nuXmv model checker for the corresponding SMV model. The workflow of Ver2Smv tool is illustrated and tested on some commonly used sequential circuit designs.