Algorithm for phase accumulator synthesis for applications in DDS

An algorithm for area-speed optimization in phase accumulator synthesis is presented here. Digital Direct Synthesis (DDS) requires an efficient phase accumulator as its main functional block. However, fast phase accumulators are very area demanding and the trade-off between area and speed is very critical. Implementation of phase accumulators with FPGA's and/or ASIC's should consider the approach presented here for optimization and synthesis.