A VLSI neural network classifier based on integer-valued weights

The VLSI-friendly constraint based decomposition (VCBD) algorithm guarantees construction of neural network classifiers with a user-chosen maximum neuron fan-in and weight values confined to a narrow band of integers. Networks with these characteristics can be efficiently implemented in VLSI. This paper presents the design of a CMOS neuron that fully exploits the characteristics of solutions produced by VCBD. The limited integer weight range enables efficient use of current-mode techniques for addition and multiplication operations within the neuron. Weights are stored in digital form without quantization error. A simple current comparator is used to provide the neuron output. Circuit operation has been verified using SPICE and these simulation results are included.