5-bit 100MHz two-phase delay-line based ADC for DC-DC converter

A 5-bit 100MHz novel analogue to digital converter (ADC) based on two-phase delay-line for DC-DC converter is proposed. Different from conventional architectures, the proposed ADC utilizes both rising and falling edges of the delay line to perform coarse and fine quantization respectively. The ADC implemented in 0.18-μm CMOS process gives a good linearity with INL of 0.8LSB and DNL of 0.54LSB and shows a high area and power efficiency.