Research on High Performance Frequency Synthesizer in Radio Frequency Integrated Circuits

With the popularization of broadcasting networks, telecommunication networks, and Internet triple play services, broadband requirements have been proposed for transceivers in wireless communication systems. Frequency source is an important part of the RF transceiver, which is usually chosen as the source of the transceiver frequency reference source. Therefore, the development of ultra-wideband, high stability, low phase noise, and low spurious performance of the frequency synthesizer is of great significance. This paper firstly analyzed the transmission process of noise in phase-locked loop by establishing a linear mathematical model of phase locking loop (PLL), and then studied the main factors affecting the phase noise and spurious performance in the application design. In order to meet the demand of triple-miniaturized RF front end, an integrated phase-locked chip is used to design a frequency synthesizer, where the output frequency of the two channels ranges from 137.5 MHz to 4.4 GHz. In order to meet the engineering application requirements, the frequency synthesizer is designed with a host computer to achieve the programmable control of the output frequency and output power. Finally, the optimized design of a wideband frequency synthesizer is provided to make up for the lack of performance of the integrated phase-locked chip design, of which the output frequency range is 31.25 MHz ~8 GHz, including basic PLL module circuit, power control module circuit, and frequency expansion module circuit.