AWEDF: An Architecture-Aware Execution and Debugging Workflow for a Highly Reliable Chip

As the technology node of the semiconductor chip enters the nano region, which can help very large scale integration (VLSI) circuits achieve better integration of production density which are companied with faster system operation speed, the embedded industry has been significantly boosted up. Despite the embedded industry trend to embrace the nano region technology, research is lacking on combining the architecture of the chip with the specific workflow to enhance the performance. This paper illustrates a system, focusing on a specific chip, that provides an execution and debugging workflow with a visibility interface to allow user access and operate. Since the existing workflow is primarily applied to common system-on-chip (SoC), and for chips requiring high reliability and execution and energy efficiency that make it difficult to execute programs with good performance, a workflow designed for the unique hardware architecture of the chip is proposed to make good use of hardware. Apart from the high performance of the system, the user-friendly condition is taken into consideration to reduce the developing difficulties. When assessing systems, while correctness,execution and energy efficiency are guaranteed, and, due to the design of workflow, users can conveniently operate the chip even for a beginner, while consuming roughly the same time as or even slightly less time than programming directly on the chip.