CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems

Continued transistor scaling and increasing power density have led to considerable increase in fault rates in silicon nanotechnology-based real-time systems. Instead of fixing everything at the hardware layer, cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates. The effectiveness (Coverage, Fault-Masking, and Recovery) and overheads (Execution time, Energy and Cost) of each fault-tolerance technique vary with the layer and the frequency at which it is implemented. Therefore, appropriate modeling of fault-mitigation methods is necessary for efficient cross-layer design space exploration (DSE). To this end, we propose a first-order framework for analyzing the effects of implementing fault-tolerance across multiple layers. We also propose a Markov-chain based methodology for analytical modeling of fault-mitigation methods and their interlayer interaction. As a case-study, we model some generic fault-mitigation methods and provide detailed modeling of typical application execution involving fault-mitigation at different layers.