A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias

A low retention Vmin 6T-SRAM is realized in 40nm CMOS technology under source bias condition. A high density (HD), ultra-low leakage (ULL) 6T SRAM cell with an area of 0.242um2 is used. We could reduce the retention Vmin of SRAM array to 0.6V using adaptive source bias scheme. Source bias is applied to achieve ultra-low leakage during standby mode of operation. Source bias results in loss of stability due to reduced effective rail-to-rail voltage of memory cell and hence becomes difficult to reduce the retention Vmin of SRAM. An adaptive source bias scheme is used to apply reduced source bias selectively for low retention noise margin (RNM) conditions. We could reduce the retention Vmin by 100mV to 0.6V compared to 0.7V realized with the conventional scheme. We could reduce the leakage at FF/125°C by 30 percent due to reduction of Vmin from 0.7V to 0.6V. At TT/0.6V/25°C, we could achieve the target leakage of 0.5pA/Cell during standby mode of operation.