Standard cell camouflage method to counter silicon reverse engineering

Payment and identification IDs using smart cards technology are vulnerable to a physical attack by reverse engineering the netlist of an embedded integrated circuit. An attacker gains access to a netlist by de-packaging and delayering a chip and processing its micrograph images. We proposed a low performance impact and novel method to obfuscate gates by using a current digital design flow with a layout standard cell generator to obfuscate non-critical paths. Results indicate that at cell and block level, a 15% timing and power overhead is incurred in applied worst-performance benchmarks. After applying the method to a set of benchmark circuits, results shown a 40% average obfuscation, or not detected gates, of the resultant netlist.