Fast computation of FFT in OFDM system

The FFT processor is an essential part utilized for implementing the frameworks of OFDM. Due to its computational necessities, it involves large area and devours high power if implemented in hardware. In this paper, a low power and area efficient pipelined FFT processor using higher radix architecture and folding transformation is presented. The implemented low power FFT has a simple structure as that of radix 2 while utilizing the advantages of higher radix architecture. Higher radix algorithm minimizes the number of multiplication with twiddle factor which in turn reduces the large power utilization in FFT. Radix 2
²
multipath feedforward architecture is proposed in this paper. As various sequence are computed parallel, a high throughput can be achieved. Hardware resources needed for the presented architecture is much less than the multipath feedback architecture. Reduced chip area and lower power consumption are the merits of this FFT processor. Verilog coding for designed architecture is simulated and synthesized in Xilinx ISE Design Suite 12.1.