Performance analysis of an efficient technique for ordering programs into multiple processors architectures

During these years, applications such as telecommunications, signal processing, digital communication with advanced features (Multi-antenna, equalization...) witness a rapid evaluation accompanied with an increase of user exigencies in terms of latency, power of computation... To satisfy these requirements, researchers work hard to adduce an efficient scheduling for hardware/software applications; where hardware is composed of multiple processors and software is represented by models of computation, synchronous dataflow (SDF) graph for instance. In this paper, we present a performance analysis of our proposed approach that calculates the best number of processors required for the scheduling process. Our proposed algorithm was evaluated by using heuristics for the scheduling process. We compared the results obtained from different scenarios. Then, we showed that the combination of our proposed algorithm with heuristics gives the best schedule in terms of speed up, efficiency and number of processors.