An optimal scheduling algorithm for data parallel hardware architectures

The problem of dataflow applications scheduling on multi-core architectures is notoriously difficult. This difficulty is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, execution time, consumption, energy, etc. Having an optimal scheduling on multi-cores DSP (Digital signal Processors) platforms is a challenging task. In this context, we present a novel technique and algorithm in order to find a valid schedule that optimizes the key performance metrics such as the latency. Our contribution is based on Satisfiability Modulo Theories (SMT) solver technologies which is strongly driven by the industrial applications and needs. We use an approach which is based on the synchronous and hierarchical behavior of both Simulink and synchronous dataflow. Whence, results of running the scheduler using our proposed SMT solver algorithm refinements produce an optimal scheduling in terms of latency and numbers of cores.