Low-power correlator architectures for wideband CDMA code acquisition

This paper concerns low-power design of a digital correlator to be used for cell synchronization in a direct spread code division multiple access (DS-CDMA) receiver. The first step in such a synchronization process is to determine the location of a periodically occurring marker (say N bits long, where N may be as large as 256) transmitted by all transmitters (base stations) in the system. This has to be done using a sliding window correlator matched to the marker pattern. Since the marker is a +1/-1 sequence, the matched filter operation involves additions and sign flip operations, but no multiplications. However, since the chip rates in typical CDMA systems are several MHz, the correlation operation consumes several giga adds per second. A straightforward implementation of this device (an N tap delay line with N adders) would be inefficient both in terms of area as well as power. We investigate a simple architecture that involves breaking the correlator into multiple partial correlations, storing the partial correlations in SRAM, and accumulating the partial results at each step. The size of the partial correlations is a parameter of the architecture; we investigate various values for this parameter and show how the estimated power of the circuit varies with the parameter. We compare our approach with other digital as well as analog approaches that have been used for such a matched filter. Finally, we discuss correlator architectures for efficiently exploiting any structure that may be present within the marker sequence.