A fast, affordable and extensible FPGA-based synthetic Ethernet traffic generator for network evaluation

Development of widespread high-speed networks accelerates the research of Ethernet test, for which testing new algorithm is important. As a result, generating traffic is indispensable to hardware test, which may contain some feature such as number of TCP or UDP flows, payload content of frames and packet sizes. When data rate of traffic aims to the level of Gb/s, this task cannot be finished only with PC, which work by Linux kernel. Even though there are some hardware achievement for this task, they are some expensive and not affordable for daily research of network evaluation. We propose a solution in this paper and describe an affordable implementation of Ethernet traffic generator for network evaluation which is FPGA-based and work in rate of 10 Gb/s with a operation interface designed in software to upper computer. The design is affordable because of it can work on a board including a 10GbE interface and an FPGA chip, which is very easy to get and can accurately configure by upper computer.