High speed low power dual-edge triggered D flip-flop

In this paper, a low power and high speed dual-edge triggered D flip-flop has been presented. The proposed design reduces the power dissipation and improves the delay. So the overall power-delay product is improved. The power dissipation observed is 17μW and delay observed is 91psec. The PDP is 1.59fJ which outperforms the designs reported in literature. The simulation results has been carried out in Cadence Virtuoso Analog Design Environment in UMC .18μm technology. The proposed design has been compared on different frequencies and voltages.