Design and implementation of RADIX-8 based 32-bit pipelined multiplier by using CLA

Arithmetic operations play a crucial role in signal processing applications, micro processors, and micro controllers. Multiplication operation is widely used in Digital Signal Processing (DSP) modules like Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) and etc. Existed design generating partial products using RADIX-4 Modified Booth Encoding (MBE) and partial products addition is done by using Wallace tree approach with Carry Save Adder (CSA). Now we modify above design, RADIX-4 MBE is replaced with RADIX-8 MBE for partial products generation and Wallace CSA tree is replaced with CLA tree for partial products addition. In both designs pipelining technique is involved. Performance comparison between existed RADIX-4 pipelined multiplier and RADIX-8 pipelined multiplier with above addition approaches, the modified method yields considerable moderate critical path delay, area and 35% reduced the power consumption. Modified design is implemented in XILINX 14.7 with FPGA technology XC3S500E-FG320-5.