Design and Implementation of Scalable Register Files Using Adiabatic Quantum Flux Parametron Logic

We have been investigating adiabatic quantum flux parametron (AQFP) as a low-power superconductor logic. In this paper, we propose multi-block power distribution and modular design for high- speed and scalable AQFP register files. In the multi-block power distribution, the entire circuit is divided into multiple blocks so as to solve clock skews. In the modular design, bit width can be increased by adding bit slices. We designed and demonstrated an 8-word and 1-bit register file adopting multi-block power distribution.