A modified three phase 5-level symmetrical multilevel inverter topology

A modified three phase symmetrical 5-level multilevel inverter structure, derived from a propounded auxiliary (AUX) inverter leg, is presented. The switch count and gate driver requirements are reduced compared to conventional topologies. An attempt is made to optimize the source requirement. The low switching frequency Selective Harmonic Elimination (SHE) method based on Bee algorithm is employed for generating gating signals. Simulations analysis is accomplished by MATLAB/SIMULINK To support the simulation results, experiment is conducted on a low power prototype.