An 82-to-108GHz −181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC

Existing ADPLLs in [1] are limited to 60GHz and are not capable of operating in the W-band. At 100GHz, DCOs become more sensitive to parasitics resulting in low frequency resolution. A high-resolution delta-sigma TDC is used to reduce quantization noise by noise-shaping in [2], but it suffers from large noise from its ring-oscillator. Moreover, the frequency tuning range of existing W-band VCOs is limited to only ~11% because using switched capacitors and varactors with low Q (<;3) is not useful. To achieve fine tuning without varactors for high Q (>8), a variable inductor, implemented with a transformer and a variable resistor, is used in [3,4]. However, the variable resistor significantly degrades the Q with a minimum value Q_min limited to Q_min≈2/k²≈2/TR, where k is the transformer coupling coefficient and TR is the tuning range. Employing a split transformer with variable resistors for wide tuning range, dual-path exponentially scaled switched-capacitor (SC) ladders for high frequency resolution, and a clock-skew-sampling delta-sigma TDC for low close-in phase noise, an 82-to-108GHz ADPLL is demonstrated in this work.