New thermal management approach for transistor-level 3-D integtration

Among various 3-D integration approaches for beyond 2-D CMOS logic, transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], vertical Si nanowire CMOS [3], and vertical FET based integrated circuit [4] holds most promise. However, such integration approaches face thermal management challenges, since stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we propose generic physical level heat management features transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. These structures are generic and can be applied to any transistor level 3-D integration approaches. Extending our previous work on Skybridge [8], we perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.