Layout based electro-thermal simulation setup

In this work we demonstrate the use of an electro-thermal simulation software to simulate the thermal resistance of SiGe HBTs. The method uses a co-simulation of a circuit simulator and a thermal simulator. The thermal model is automatically extracted from the chip layout and the provided material stack. After adaption of the thermal properties of silicon we achieve an agreement between measurement and simulation of better than 5 %. The complete simulation flow is integrated in a design kit which allows the designer to model the electro-thermal performance of the integrated circuits at design level.