Novel symmetric and asymmetric topology of multilevel inverter with reduced number of switches

In this paper, a new multilevel inverter topology which can be operated in both symmetrical and asymmetrical configurations has been proposed. In order to produce all steps of voltage at output, four different algorithms are proposed to find the value of DC sources. The proposed topology reduce switch count, gate driver circuits, total voltage blocking capability and isolated DC voltage sources which leads to reduction in installation space and cost. For switching purpose multiple carrier PWM strategy has been used. Simulation results have been presented for 9-level, 17-level and 53-level operation of proposed inverter using MATLAB/SIMULINK software and the feasibility of topology has been validated experimentally.