Low power positive-edge triggered D-type flip-flop

In this paper, a low power positive-edge triggered D flip-flop has been presented. The proposed design reduces the power dissipation when the data rate is low. The overall powerdelay product is improved at/or below 50% switching activity. Based on the simulation results using Cadence Virtuoso Analog Design Environment in UMC 0.18μm technology, outperforms the designs reported in previous papers at or below switching activity of 50% The proposed design is operated upon the clock frequency of 250MHz.