Design and implementation of FIR filter with modified product accumulation block using booth multiplier

In the multiplierless realization of finite impulse response (FIR) filters in transposed direct form (TDF), it is observed that the adders present in the product accumulation block named as structural adders (STAs) are the major contributor to the overall logic complexity. In this paper we propose a novel design of FIR filter structure. In the proposed structure the multiple constant multiplications unit (MCMU) is divided into sub-MCMU blocks and the partial products obtained from them are added in the product accumulation unit using booth multiplier. As a result, half of the long word length STAs are replaced with adders which are named as pre-structural adders (PSTAs). PSTAs have relatively shorter word length. The HDL synthesis results shows that the delay to the output of the proposed 8-tap filter gains an improvement of 68.26% over the conventional method. The implementation is done using Verilog HDL. Simulation and synthesis are done with Xilinx ISE tool.