Comparative analysis of single precision floating point multiplication using compressor techniques

Compressor models are used to perform arithmetic operations like multiplication, addition etc. in digital signal processing applications such as Fast Fourier Transform, Convolution and Filtering. In order to achieve the high speed, the optimization takes place in all abstraction levels. In this paper, single precision floating point multiplication is developed using different compressor architectures to achieve high speed. Further, first, floating point multipliers are developed with normal 4:2 conventional compressors using XOR gates and further the same multipliers are developed using modified Compressors with XOR-XNOR gates and Multiplexers to achieve optimized delay and area. All the models are coded with Verilog HDL and implemented using Xilinx ISE.