A two stages MMIC CDMA power amplifier using harmonic load pull simulation technique

This paper reports a two stages MMIC power amplifier with low quiescent current and high power added efficiency (PAE) for PCS CDMA application. Based on an accurate large signal PHEMT model, a systematic load (source) pull simulation scheme was developed to design the linear power amplifier. The two stages PCS CDMA PA attained over 40% PAE, 28.5 dBm output power and 18.5 dB gain at -45 dBc adjacent channel power rejection (ACPR) under a supply voltage of 3.6 V. The total quiescent current is only 110 mA. The chip size of the amplifier is 0.86/spl times/1.24 mm and assembled in 16 pins HS-SSOP plastic package.