Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization

In recent years, spin-transfer torque random access memory (STT-RAM) has been widely studied as a promising candidate to replace DRAM because of its fast access time, high endurance, and good CMOS compatibility. The improvement of tunneling magneto-resistance ratio (TMR) of magnetic tunneling junction (MTJ) also makes it possible to store more than one bit in a STT-RAM cell, namely, a multi-level cell (MLC) STT-RAM cell. One example is connecting two MTJs with different sizes in series to form four different resistance states that represent two bits in a memory cell. Very recently, Biaxial MTJ was proposed to realize four stable resistance states in a single MTJ. This technology greatly relaxes the driving capability requirement of select transistor and hence, increases the integration density of the MLC STT-RAM cells by reducing the size of the select transistor. In this paper, we developed the first device model of biaxial MTJ that can capture the switching transience between its four different states. We also validated our developed model against a manufactured biaxial MTJ device.