Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks

Stochastic Computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. In a bit-stream representing probability x, each bit has probability x of being 1. Using this simple assumption, SC can perform complex tasks with much smaller hardware footprints compared to conventional binary methods: e.g., a simple AND gate can perform multiplication between two uncorrelated bit-streams. Previous methods on SC circuits either relied on (1) randomness in the input bit streams, or (2) more recently, performing full convolution of deterministic streams to achieve exact computation results. The problem with the first method is that it introduces high random fluctuations and hence high variability in the results. The second method results in exponential increase in the length of the bit stream as circuit depth increases. Both of these methods suffer from very long latencies and neither is readily adaptable for parallel implementations. Our work presents a significant improvement over previous work: it provides a deterministic parallel bit shuffling network that can use a simple deterministic thermometer encoding of data, resulting in zero random fluctuation and high accuracy, yet keeping the output bit stream length constant. We use core “stochastic” logic circuits that do not employ constant coefficients, making them significantly smaller than traditional stochastic logic that potentially use a significant amount of resources to generate such constant coefficients. We show results on feed-forward and feedback circuits and show that our method on average has an area × delay value that is 10.6x smaller than of conventional binary and 7.9x smaller than previous stochastic work at 10-bit binary resolutions.