Basic CMOS Gate Design by Mixed-Mode Analysis of Step-Channel TMDG-MOSFET

This paper introduces a novel MOSFET design having a Step-channel Triple Material with Double Gate (STMDG). Our work commences with the design of a STMDG MOSFET using Technology Computer Aided Design (TCAD) simulation tool Sentaurus. We have created two structures of STMDG-MOSFET. In first design (Type-I) the structure has a substrate whose thickness reduces from the source towards the drain. The second design (Type-II) has a tapering from both the source and drain ends wherein the central substrate region is the thinnest. The performance of these devices are contrasted against a typical Linear-channel Triple Material Double Gate MOSFET (LTMDG MOSFET). Both electrical and analog performances are used to analyze the effectiveness of the proposed structure. Using the IV characteristics, we obtain threshold voltage, on-off current ratio, subthreshold slope (SS) and drain induced barrier lowering (DIBL). Next we evaluate the electrostatic-potential and electric-field plots from electrical performance. Further the analog performance of the device is estimated from the transconductance, capacitance, gain and cut-off frequency versus gate voltage plots. Finally we have designed CMOS inverter, NAND and NOR gates using the STMDG Type-I and Type-II MOSFETs and optimized its voltage transfer characteristics (VTC) and switching characteristics to show the utility of our device.