Crosstalk-centric designing using graphene based multi-line bus architecture

This research paper analyzes and compares the propagation delay under the influence of dynamic crosstalk of Cu, MWCNT and MLGNR interconnects. A multi-line bus architecture, driven by a CMOS driver is employed to demonstrate the crosstalk effect. An equivalent single conductor (ESC) model is introduced that accurately takes into account the diameter dependent conducting channels and mean free path. HSPICE simulations are performed to analyze the crosstalk induced delay under the out-of-phase switching scenario. Each interconnect line of a 5-line bus architecture is represented by equivalent models of Cu, MWCNT and MLGNR. The interconnect length is varied in the range of 30 μm to 90 μm. Irrespective of interconnect lengths, it is observed that the crosstalk induced delay drastically reduces for MLGNR with more number of layers compared to equivalent Cu and MWCNT interconnect. On an average, the MLGNR with more number of layers possesses 35.1% and 20.6% improved crosstalk induced delay compared to equivalent Cu and MWCNT interconnects, respectively.