Design and development of FPGA-based FFT Co-processor for Synthetic Aperture Radar (SAR)

Synthetic Aperture Radar (SAR) is a well-established and powerful microwave remote sensing technique which is capable of obtaining an image based on the reflectivity of a target or earth surface in all weather. In the application of digital SAR processing, signal processing poses a significant challenge because of its stringent computation power and data storage requirements. A high resolution SAR system captures the return echoes and yields huge amount of raw data. In the algorithm layer, Range Doppler Algorithm (RDA), Chirp Scaling Algorithm (CSA) and Omega-K Algorithm (ωKA) are thorough studied and compared in this research work. It is important to examine Fast Fourier Transform (FFT) in the context of SAR as it plays a major role in convolution operations such as matched filtering. It is essential to treat the FFT as a coprocessor during the hardware implementation of SAR processor. This paper highlights the design and development of an FGPA-based pre-processing unit for real-time SAR imaging. Particularly, an efficient FFT co-processor has been designed and developed. The proposed co-processor architecture significantly reduced the hardware resources while achieving the reasonably high processing speed. A detailed literature review is conducted on the FPGA-based implementation of FFT, the performance of these coprocessors are compared in term of 7 metrics. The proposed FFT co-processor is compared with the literature one. From the evaluation, the proposed coprocessors not only showing the promising and satisfactory results in the time-frequency transformation but also in the aspects of hardware utilizations, timing performance and precision.