Design of Digital Satellite Processors: From Communications Link Performance to Hardware Complexity

Latest developments in satellite communications encompass semitransparent transponder architectures. Such architectures have potentials: 1) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards and 2) to support dynamic reconfiguration of connectivity plans. In this frame, significant on-board digital processing is involved, which calls for careful system modeling and accurate digital hardware design to achieve feasible tradeoffs between hardware efficiency and overall link-budget performance. In our recent works, we have proposed and validated a quantitative framework for performance analysis and design of digital transparent processors (DTPs): the model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the nonideal behavior (e.g., quantization and rounding errors and linear distortions) of the various DTP segments. This paper complements the previous works by providing: 1) an explicit computation of implementation complexity of a DTP and 2) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital hardware (HW) components in the DTP. Through numerical examples, we demonstrate that, given a requirement on the overall link budget performance in contexts of practical interest, significant differences in HW complexity are obtained for different design choices.