Real-time simulation of an asymmetrical phase domain synchronous machine on FPGA

This paper presents an asymmetrical phase-domain synchronous machine model using sub-microsecond sampling time on FPGA. Previous literature has presented synchronous machine simulated on FPGA where all three phases are symmetrical, allowing a representation in the dq-domain, and reducing the complexity of the equations to be solved. When a fault occurs within the machine winding, the machine's parameters become asymmetrical, in which case, classical dq-domain representation is inaccurate. There are two innovations in the proposed method. First, a finer representation of the machine is used, and second, the FPGA implementation does not require to invert a matrix during discretizations. Results from the proposed model are validated by comparing the ones obtained using an offline simulation with a variable-step solver.