A new model of low power dynamic logic circuit

Dynamic CMOS circuits are frequently used in low power and high-performance VLSI systems. Limitations of noise margin, leakage current are main challenging element of dynamic circuit design. In this work, a new model keeper circuit is proposed that optimizes the noise tolerance and power dissipation. Expansive simulation analysis by employing LTSpice tools using 32nm PTM technology establish the validity and robustness of the proposed work.