A review on resource efficient polar decoders-present and past

In this paper, the ground work on polar decoder is concentrated by studying the various existing techniques in the design of polar decoders. The goal of channel coding is to detect and correct errors that appear during the transmission of information. The polar codes have an explicit construction and low-complexity encoding. Moreover, polar codes are provably capacity achieving over a wide range of channels, making them very attractive from a theoretical perspective. The broader categories of polar decoders as belief propagation and successive cancellation varies by the fact that the former based on inherent high parallelism and hence much faster than the latter with a series of interlaced steps with low decoding complexity and increased throughput in spite of its high decoding latency. This paper reviews the hardware implementation of polar decoders in very large scale integration perspective to explore a low complex architecture with minimum resource utilization with respect to processing and storage elements. The comparative analysis on the performance of existing polar decoders based on field programmable gate array implementation of different technologies such as 90nm, 65nm, 40nm and 28nm with respect to the number of lookup tables, flip-flops and throughput are presented.