FPGA implementation of a phaselet method for high speed distance relaying — Preliminary results

Fault clearing time is critical to the safety of power system equipment. Most state-of-art distance relays operate at the speed of one cycle or even longer. There are a few sub-cycle algorithms such as half-cycle type Fourier, least error square, traveling wave, and wavelet type methods. This paper utilizes a sub-cycle (phaselet) method for estimation. The algorithm and testing with IEC 61850 Sampled Value and GOOSE communication protocols was discussed in detail in the recently accepted paper by the authors in the IEEE Transactions on Smart Grids [1]. The main focus of this paper is on the hardware implementation of the phaselet method on field programmable gate arrays (FPGAs) to achieve high speed and the hardware-in-the-loop testing. The FPGA implementation of the method helps in parallelizing the algorithm and provides fast computation speed compared to sequential execution on digital signal processor (DSP). The algorithm is implemented on Xilinx Virtex 6 board. The FPGA relay is tested using hardware-in-the-loop simulations with a real time digital simulator (RTDS).