An efficient algorithm for intra prediction in HEVC/H.265 standard for 16×16 pixels

The present world needs an efficient cutting edge technology for processing high resolution videos. This leads to the development of new compression technique known as High Efficiency Video Coding (HEVC) or H.265 Standard. The HEVC works on 4K and 8K video applications. In this paper a new parallel and pipelined hardware accelerator is implemented which is highly efficient for 16 × 16 Intra Prediction blocks. The Parallel and Pipelined architecture speeds up the process of prediction and also minimizes the time required for accessing the data from the memory. The given architecture design reduces Area, Power and Delay. The results when compared with different FPGA versions shows that our architecture consumes 138 slice registers and 519 LUTs in ZYNQ FPGA for 16 × 16 pixels.