Design and simulation of low drop out voltage using 180nm CMOS technology

The Low Drop-out Voltage (LDO)regulators more used in a present electronic industry since LDOs are one of the subsystems of the power management unit. The growing demand of mobile battery-operated products and portable devices like laptop, tabs etc increases the use of LDO as power management modules in System On Chip (SOC) design. The LDO's are used to protect sensitive analog blocks from the coupled power supply noise as LDO's Power Supply Rejection Ratio (PSRR) performance is high. The supply voltage and low quiescent current in LDO defines the battery life. The objective of the proposed work is designed the LDO using folded cascode amplifier and compared the simulated result with CMOS differential amplifier (0.5um). The LDO is designed by using 180nm CMOS technology with supply voltage of 3.3V and reference voltage is 1.2V. Simulation results gives LDO full load current 10uA to 5mA in transient response with a low drop-out voltage of <;200mV and the measured settling time is <;500ns in full load condition.